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IMAGE SENSOR SOLUTIONS
DEVICE PERFORMANCE SPECIFICATION
KODAK KAI-1010 KODAK KAI-1010M KODAK KAI-1011CM Image Sensor
1008 (H) x 1018 (V) Interline Transfer Progressive Scan CCD
October 28, 2002 Revision 8
KAI-1010/1011 Rev 8 *
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IMAGE SENSOR SOLUTIONS
Table of Contents
Features ..........................................................................................................................................................4 Features ..........................................................................................................................................................4 Description .....................................................................................................................................................5 Architecture....................................................................................................................................................5 Image Acquisition ..........................................................................................................................................5 Charge Transport ...........................................................................................................................................6 Output Structure.............................................................................................................................................7 Electronic Shutter...........................................................................................................................................8 Color Filter Array (optional, for KAI-1011CM only) ...................................................................................8 Packaging Configuration ...............................................................................................................................9 Pin Description.............................................................................................................................................10 Absolute Maximum Range ..........................................................................................................................12 DC Operating Conditions ............................................................................................................................13 AC Clock Level Conditions.........................................................................................................................14 AC Timing Requirements for 20 MHz Operation .......................................................................................15 Frame Timing - Single Register Readout ..........................................................................................16 Line Timing - Single Register Readout .............................................................................................17 Pixel Timing - Single Register Readout ............................................................................................18 Electronic Shutter Timing - Single Register Readout........................................................................19 Frame Timing - Dual Register Readout.............................................................................................20 Line Timing - Dual Register Readout................................................................................................21 Pixel Timing - Dual Register Readout...............................................................................................22 Fast Dump Timing - Removing Four Lines ......................................................................................23 Binning - Two to One Line Binning .................................................................................................24 Timing - Sample Video Waveform ...................................................................................................25 Image Specifications ....................................................................................................................................26 Electro-Optical for KAI-1011CM......................................................................................................26 Electro-Optical for KAI-1010M ........................................................................................................28 CCD ...................................................................................................................................................31 Output Amplifier @ VDD = 15V, VSS = 0.0V ....................................................................................31 General ...............................................................................................................................................32 Defect Classification ....................................................................................................................................34 Climatic Requirements.................................................................................................................................35 Quality Assurance and Reliability ...............................................................................................................35 Ordering Information ...................................................................................................................................36
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Figures
Figure 1 Functional Block Diagram ..............................................................................................................4 Figure 2 KAI-1011CM ..................................................................................................................................5 Figure 3 True 2 Phase CCD Cross Section ....................................................................................................6 Figure 4 Output Structure ..............................................................................................................................7 Figure 5 CFA Pattern .....................................................................................................................................8 Figure 6 Device Drawing - Die Placement ....................................................................................................9 Figure 7 Pinout Diagram Top View.............................................................................................................11 Figure 8 Recommended Output Structure Load Diagram ...........................................................................13 Figure 9 Frame Timing - Single Register Readout ......................................................................................16 Figure 10 Line Timing - Single Register Output .........................................................................................17 Figure 11 Pixel Timing Diagram - Single Register Readout.......................................................................18 Figure 12 Electronic Shutter Timing Diagram - Single Register Readout ..................................................19 Figure 13 Frame Timing - Dual Register Readout ......................................................................................20 Figure 14 Line Timing - Dual Register Output ...........................................................................................21 Figure 15 Pixel Timing Diagram - Dual Register Readout .........................................................................22 Figure 16 Fast Dump Timing - Removing Four Lines ................................................................................23 Figure 17 Binning - 2 to 1 Line Binning......................................................................................................24 Figure 18 Sample Video Waveform at 5MHz .............................................................................................25 Figure 19 Nominal KAI 1011CM Spectral Response .................................................................................27 Figure 20 Nominal KAI-1010M Spectral Response....................................................................................28 Figure 21 Angular Dependence of Quantum Efficiency .............................................................................29 Figure 22 Frame Rate versus Horizontal Clock Frequency.........................................................................30 Figure 23 Typical KAI-1010M Photoresponse............................................................................................32 Figure 24 Example of Vsat versus Vsub......................................................................................................33
Tables
Table 1 Package Pin Assignments ...............................................................................................................10 Table 2 Absolute Maximum Ranges............................................................................................................12 Table 3 DC Operating Conditions ...............................................................................................................13 Table 4 AC Clock Level Conditions............................................................................................................14 Table 5 AC Timing Requirements for 20 MHz Operation ..........................................................................15 Table 6 Electro-Optical Image Specifications KAI-1011CM .....................................................................26 Table 7 Electro-Optical Image Specifications KAI-1010M ........................................................................28 Table 8 CCD Image Specifications..............................................................................................................31 Table 9 Output Amplifier Image Specifications ..........................................................................................31 Table 10 General Image Specifications .......................................................................................................32 Table 11 Climatic Requirements .................................................................................................................35
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Features
* * * * * * * * Front Illuminated Interline Architecture 1008 (H) x 1018 (V) Photosensitive Pixels 9.0m(H) x 9.0m(V) Pixel Size 9.1 mm(H) x 9.2 mm(V) Photosensitive Area Progressive Scan (Noninterlaced) Electronic Shutter Integral RGB Color Filter Array (optional) Advanced 2 Phase Buried Channel CCD Processing * * * * * * * On-Chip Dark Reference Pixels Low Dark Current Patented High Sensitivity Output Structure Dual Output Shift Registers Antiblooming Protection Negligible Lag Low Smear (0.01% with microlens)
4 dark lines at bottom of image V1 V2 6 dark columns KAI-1010 Active Image Area: 1008 (H) x 1018 (V) 9.0 x9.0 m2 pixels 10 dark columns V1 V2
VRD R VDD VOUTA VSS/OG VDD VOUTB VSS/OG WELL VSUB
2 dark lines at top of image
Horizontal Register A 6 dummies Horizontal Register B 2 dummies
H1A H2
H1B
Figure 1 Functional Block Diagram
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Description
The KAI-1010 series is a high resolution charge coupled device (CCD) image sensor whose noninterlaced architecture makes it ideally suited for video, electronic still and motion/still camera applications. The device is built using an advanced true two-phase, doublepolysilicon, NMOS CCD technology. The p+npnphotodetector elements eliminate image lag and reduce image smear while providing antiblooming protection and electronic-exposure control. The total chip size is 10.15 (H) mm x 10.00 (V) mm. The KAI-1010 comes in monochrome and color versions, both with microlens for sensitivity improvement.
Image Acquisition
An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the photodiode's charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming.
Device KAI-1010 KAI-1010M KAI-1011CM
Color No No Yes
Microlens No Yes Yes
Figure 2 KAI-1011CM Architecture
The KAI-1010 consists of 1024 x 1024 photodiodes, 1024 vertical (parallel) CCD shift registers (VCCDs), and dual 1032 pixel horizontal (serial) CCD shift registers (HCCDs) with independent output structures. The device can be operated in either single or dual line mode. The advanced, progressive-scan architecture of the device allows the entire image area to be read out in a single scan. The active pixels are arranged in a 1008 (H) x 1018 (V) array with an additional 16 columns and 6 rows of lightshielded dark reference pixels.
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Charge Transport
The accumulated or integrated charge from each photodiode is transported to the output by a three step process. The charge is first transported from the photodiodes to the VCCDs by applying a large positive voltage to the phase-one vertical clock (oV1). This reads out every row, or line, of photodiodes into the VCCDs. The charge is then transported from the VCCDs to the HCCDs line by line. Finally, the HCCDs transport these rows of charge packets to the output structures pixel by pixel. On each falling edge of the horizontal clock, oH2, these charge packets are dumped over the output gate (OG, Figure 4) onto the floating diffusion (FDA and FDB, Figure 4). Both the horizontal and vertical shift registers use traditional two-phase complementary clocking for charge transport. Transfer to the HCCDs begins when oV2 is clocked high and then low (while holding oH1A high) causing charge to be transferred from oV1 to oV2 and subsequently into the A HCCD. The A register can now be read out in single line mode. If it is desired to operate the device in a dual line readout mode for higher frame rates, this line is transferred into the B HCCD by clocking oH1A to a low state, and oH1B to a high state while holding oH2 low. After oH1A is returned to a high state, the next line can be transferred into the A HCCD. After this clocking sequence, both HCCDs are read out in parallel. The charge capacity of the horizontal CCDs is slightly more than twice that of the vertical CCDs. This feature allows the user to perform two-to-one line aggregation in the charge domain during V-to-H transfer. This device is also equipped with a fast dump feature that allows the user to selectively dump complete lines (or rows) of pixels at a time. This dump, or line clear, is also accomplished during the V-to-H transfer time by clocking the fast dump gate.
Pixel Pn +V -V
Pixel Pn+1 -V +V
Q1
Q2
Direction of Transfer Figure 3 True 2 Phase CCD Cross Section
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Output Structure
Charge packets contained in the horizontal register are dumped pixel by pixel, onto the floating diffusion output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential change is determined by the expression Vfd=Q/Cfd. A three stage source-follower amplifier is used to buffer this signal voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of V/e-. After the signal has been sampled off-chip, the reset clock (oR) removes the charge from the floating diffusion and resets its potential to the reset-drain voltage(VRD).
VDD
R
RD
VOUT A
FDA (n/c)
HCCDA
VSS & OG
HCCDB
FDB (n/c)
VOUT B
VWELL VS UB
Figure 4 Output Structure
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Electronic Shutter
The KAI-1010 provides a structure for the prevention of blooming which may be used to realize a variable exposure time as well as performing the anti-blooming function. The anti-blooming function limits the charge capacity of the photodiode by draining excess electrons vertically into the substrate (hence the name Vertical Overflow Drain or VOD) . This function is controlled by applying a large potential to the device substrate (device terminal SUB). If a sufficiently large voltage pulse (VES 40V) is applied to the substrate, all photodiodes will be emptied of charge through the substrate, beginning the integration period. After returning the substrate voltage to the nominal value, charge can accumulate in the diodes and the charge packet is subsequently readout onto the VCCD at the next occurrence of the high level on V1. The integration time is then the time between the falling edges of the substrate shutter pulse and V1. This scheme allows electronic variation of the exposure time by a variation in the clock timing while maintaining a standard video frame rate. Application of the large shutter pulse must be avoided during the horizontal register readout or an image artifact will appear due to feedthrough. The shutter pulse VES must be "hidden" in the horizontal retrace interval. The integration time is changed by skipping the shutter pulse from one horizontal retrace interval to another. The smear specification is not met under electronic shutter operation. Under constant light intensity and spot size, if the electronic exposure time is decreased, the smear signal will remain the same while the image signal will decrease linearly with exposure. Smear is quoted as a percentage of the image signal and so the percent smear will increase by the same factor that the integration time has decreased. This effect is basic to interline devices.
Color Filter Array (optional, for KAI1011CM only)
6 BLACK COLUMNS
B
G
R
B
G
R
G
G
B
B
G
G
R
G
R
G
2 BLACK LINES
OUTPUT
Figure 5 CFA Pattern
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Packaging Configuration
Figure 6 Device Drawing - Die Placement
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Pin Description
PIN NO. 1,5,14,16,20,21 2, 24 3, 23 4 6 7 8 9 10 11 12 13 15 17 18 19 22 SYMBOL GND oV1 oV2 SUB FDG VDD VOUTA VSS oR VRD VOUTB oH2 oH1B oH1A IDHB IDHA WELL DESCRIPTION Ground Vertical CCD Clock - Phase 1 Vertical CCD Clock - Phase 2 Substrate Fast Dump Gate Output Amplifier Supply Video Output Channel A Output Amplifier Return & OG Reset Clock Reset Drain Video Output Channel B A & B Horizontal CCD Clock - Phase 2 B Horizontal CCD Clock - Phase 1 A Horizontal CCD Clock - Phase 1 Input Diode B Horizontal CCD Input Diode A Horizontal CCD P-Well Notes 1 2 3
Table 1 Package Pin Assignments
Notes: 1. All GND pins should be connected to WELL (P-Well). 2. Pins 2 and 24 must be connected together - only 1 Phase 1 clock driver is required. 3. Pins 3and 23 must be connected together - only 1 Phase 2 clock driver is required.
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GND V1L V2L SUB GND FDG VDD VOUTA VSS R VRD
1 2 3 4 5 6 7 8 9 10 11
24 23
V1R V2R
22 WELL 21 20 19 18 GND GND IDHA IDHB
17 H1A 16 GND
Pixel 1,1
15 H1B 14 13 GND H2
VOUTB 12
Figure 7 Pinout Diagram Top View
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Absolute Maximum Range
RATING Temperature (@ 10% 5%RH) Voltage (Between Pins) DESCRIPTION Operation Without Damage Storage SUB-WELL VRD,VDD,OG&VSS-WELL IDHA,B & VOUTA,B - WELL V1 - V2 H1A, H1B - H2 H1A, H1B, H2, FDG - V2 H2 - OG & VSS R - SUB All Clocks - WELL Output Bias Current (Iout) MIN. -50 -55 0 0 0 -12 -12 -12 -12 -20 -12 ---MAX. +70 +70 +40 +15 +15 +20 +15 +15 +15 0 +15 10 UNITS C C V V V V V V V V V mA NOTES
Current
1 2 2 2 2 2 2 1,2,4 2 3
Table 2 Absolute Maximum Ranges
Notes: 1. 2. 3. 4. Under normal operating conditions the substrate voltage should be above +7V, but may be pulsed to 40 V for electronic shuttering. Care must be taken in handling so as not to create static discharge which may permanently damage the device. Per Output. Iout affects the band-width of the outputs. R should never be more positive than VSUB.
Caution: This device contains limited protection against Electrostatic Discharge (ESD) Devices should be handled in accordance with strict ESD procedures for Class 0 devices (JESD22 Human Body Model) or Class A (Machine Model). Refer to Application Note MTD/PS-0224, "Electrostatic Discharge Control" Caution: Improper cleaning of the cover glass may damage these devices. Refer to Application Note MTD/PS-0237, "Cover Glass Cleaning for Image Sensors"
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DC Operating Conditions
SYMBOL VRD IRD VSS ISS VDD Iout WELL GND FDG SUB IDHA, IDHB DESCRIPTION Reset Drain Reset Drain Current Output Amplifier Return & OG Output Amplifier Return Current Output Amplifier Supply Output Bias Current P-well Ground Fast Dump Gate Substrate Input Diode A, B Horizontal CCD MIN. 8.5 NOM. 9 0.2 0 5 15.0 5 0.0 0.0 -6.0 Vsub 15.0 MAX. 9.5 UNITS V mA V mA V mA V V V V V PIN IMPEDANCE6 5pF, > 1.2M 30pF, >1.2M 30pF, >1.2M Common 20pF, >1.2M 1nF, >1.2M 5pF, > 1.2M 5 1 1 2 3 4 NOTES
12 --------7.0 7 12.0
15.0 10 -------5.5 15 15.0
Table 3 DC Operating Conditions
Notes: 1. 2. 3. 4. 5. 6. 7. The WELL and GND pins should be connected to P-well ground. The voltage level specified will disable the fast dump feature. This pin may be pulsed to Ves=40V for electronic shuttering Electrical injection test pins. Connect to VDD power supply. Per output. Note also that Iout affects the bandwidth of the outputs. Pins shown with impedances greater than 1.2 Mohm are expected resistances. These pins are only verified to 1.2 Mohm. The operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments of these voltages.
+15V 0.1 F
5mA Vout 2N3904 or equivalent
140 1K
Buffered Output
Figure 8 Recommended Output Structure Load Diagram
Cautions: In order to obtain maximum device performance, gate protection is not provided. Extreme care must be taken in handling to prevent electrostatic discharge which may permanently damage the device. Care must be taken not to short the outputs to ground or VDD during operations.
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AC Clock Level Conditions
SYMBOL V1 DESCRIPTION Vertical CCD Clock Level Low Mid High Low High Low High Low Low High Low High Low High Low High Min. -10.0 0.0 8.5 -10.0 0.0 -7.5 2.5 -7.5 -7.5 2.5 -7.5 2.5 -6.5 -0.5 -7.0 4.5 NOM. -9.5 0.2 9.0 -9.5 0.2 -7.0 3.0 -7.0 -7.0 3.0 -7.0 3.0 -6.0 0.0 -6.0 5.0 MAX. -9.0 0.4 9.5 -9.0 0.4 -6.5 3.5 -6.5 -6.5 3.5 -6.5 3.5 -5.5 0.5 -5.5 5.5 UNITS V V V V V V V V V V V V V V V V PIN IMPEDANCE2 25nF, >1.2M
V2 H1A H1B4 H1B4 H2 R FDG3
Vertical CCD Clock 1 Horizontal CCD A Clock 1 Horizontal CCD B Clock (single register mode) 1 Horizontal CCD B Clock (dual register mode) 2 Horizontal CCD Clock Reset Clock Fast Dump Gate Clock
25nF, >1.2M 100pF, > 1.2M 100pF, > 1.2M 100pF, > 1.2M 125pF, > 1.2M 5pF, > 1.2M 20pF, > 1.2M
Table 4 AC Clock Level Conditions
Notes: 1. 2. 3. 4. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments of these voltages. Pins shown with impedances greater than 1.2 Mohm are expected resistances. These pins are only verified to 1.2 Mohm. When not used, refer to DC operating condition. For single register mode, set H1B to -7.0 volts at all times rather than clocking it.
This device is suitable for a wide range of applications requiring a variety of different operating conditions. Consult Eastman Kodak in those situations in which operating conditions meet or exceed minimum or maximum levels.
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AC Timing Requirements for 20 MHz Operation
SYMBOL tR t es t int t Vh t cd t cp t sd t sp t rd t V t H t AB t Hd t Vd t HVES DESCRIPTION Reset Pulse Width Electronic Shutter Pulse Width Integration Time Photodiode to VCCD Transfer Pulse Width Clamp Delay Clamp Pulse Width Sample Delay Sample Pulse Width Vertical Readout Delay V1, V2 Pulse Width Clock Frequency H1A, H1B , H2 Line A to Line B Transfer Pulse Width Horizontal Delay Vertical Delay Horizontal Delay with Electronic Shutter MIN 10 0.1 4 NOM 10 25 5 15 15 35 15 ------20 3 MAX UNITS nsec sec msec sec nsec nsec nsec nsec sec sec MHz sec sec nsec sec NOTES FIGURE Figure 11 Figure 12 Figure 12 Figure 9 Figure 11 Figure 11 Figure 11 Figure 11 Figure 9 Figure 10 Figure 11 Figure 14 Figure 10 Figure 10 Figure 12
1 2
10 3 ---3 25 1
----
Table 5 AC Timing Requirements for 20 MHz Operation
Notes: 1. 2. Integration time varies with shutter speed. It is to be noted that smear increases when integration time decreases below readout time (frame time). Photodiode dark current increases when integration time increases, while CCD dark current increases with readout time (frame time). Antiblooming function is off during photodiode to VCCD transfer.
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Frame Timing - Single Register Readout
1 Frame = 1024 Lines
Frame T ime
V1
V2
1022
1023
1018
1021
1022
1023
0
1
2
3
4
0
1
1019
1020
V1
t rd t Vh
V2
1021
1022
1023
0
Figure 9 Frame Timing - Single Register Readout Note : When no electronic shutter is used, the integration time is equal to the frame time.
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IMAGE SENSOR SOLUTIONS
Line Timing - Single Register Readout
V1 t V t d
V2 1 t Vd 1 2 R
H1B held low for single register operation
Line Content
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
Photoactive P ixels
Empty S R hift egister P hases
Dark Reference Pixels
Figure 10 Line Timing - Single Register Output
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Pixel Timing - Single Register Readout
1 count = 1 P ixel tH= 50ns min
H1A H2 R tR
Referenc e tc d tc p Signal tsp tsd
VOUT A
CLAMP S AMPLE
VIDEO AFT DOUBLE ER CORRELAT S ED AMPLING (INVERT ED)
Reference
Figure 11 Pixel Timing Diagram - Single Register Readout
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Signal
IMAGE SENSOR SOLUTIONS
Electronic Shutter Timing - Single Register Readout
Electronic S hutter - Frame T iming V1
V2 Integration time tint VES (S B) U
Electronic S hutter - Placement V1
V2 H1A H2 t HVE S VES (S B) U t es
Electronic S hutter - Operating Voltages
Ves VES (S B) U R eferenc e Vsub
Figure 12 Electronic Shutter Timing Diagram - Single Register Readout
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Frame Timing - Dual Register Readout
1 Frame = 512 Lines P airs
Frame T ime
V1
V2
1020,1021
1022,1023
0,1
1020,1021
2,3
4,5
6,7
0,1
2,3
1012,1013
1014,1015
1016,1017
1018,1019
V1 V2
1018,1019 1020,1021
1022,1023
1022,1023
8,9
trd tVh
0,1
Figure 13 Frame Timing - Dual Register Readout Note : When no electronic shutter is used, the integration time is equal to the frame time.
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4,5
IMAGE SENSOR SOLUTIONS
Line Timing - Dual Register Readout
t V t V t V t d V2 1 t /
V1
t Vd
1 2 R
Line Content
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
Photoactive P ixels
Empty S Register Phases hift
Dark Reference Pixels
Figure 14 Line Timing - Dual Register Output
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Pixel Timing - Dual Register Readout
1 count = 1 P ixel H1A H1B H2 R tR
Referenc e tc d tc p Signal
tH= 50ns min
VOUT A
CLAMP
tsp
S AMPLE
VIDEO AFT DOUBLE ER CORRELAT S ED AMPLING (INVERT ED)
Reference
Figure 15 Pixel Timing Diagram - Dual Register Readout
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Signal
tsd
IMAGE SENSOR SOLUTIONS
Fast Dump Timing - Removing Four Lines
V1
V2
FDG
H1A H1B
H2 R End of a Valid Line Dumped Line #1 Dumped Line #2 Dumped Line #3 Dumped Line #4 Valid Line
V2 min 0.5 sec FDG
V2 min 0.5 sec
FDG Fast Dump Rising Edge wrt V2 Falling Edge V2 max 0.1 sec FDG Fast Dump Falling Edge wrt V2 Rising Edge Fast Dump Falling Edge wrt V2 Falling Edge
Figure 16 Fast Dump Timing - Removing Four Lines
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Valid Line
IMAGE SENSOR SOLUTIONS
Binning - Two to One Line Binning
V1
V2
H1A
H1B
H2 R tV tVd tHd
Figure 17 Binning - 2 to 1 Line Binning
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Timing - Sample Video Waveform
Figure 18 Sample Video Waveform at 5MHz
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Image Specifications
All the following values were derived using nominal operating conditions using the recommended timing. Unless otherwise stated, readout time = 140ms, integration time = 140ms and sensor temperature = 40oC. Correlated double sampling of the output is assumed and recommended. Many units are expressed in electrons, to convert to voltage, multiply by the amplifier sensitivity. Defects are excluded from the following tests and the signal output is referenced to the dark pixels at the end of each line unless otherwise specified.
Electro-Optical for KAI-1011CM
SYMBOL FF Esat QEr QEg QEb Rgs PRNU PRNL PARAMETER Optical Fill Factor Saturation Exposure Red Peak Quantum Efficiency = 620nm Green Peak Quantum Efficiency = 530nm Blue Peak Quantum Efficiency = 470nm Green Photoresponse Shading Photoresponse Non-uniformity Photoresponse Non-linearity Amplifier Sensitivity MIN. NOM. 55.0 0.046 25 28 34 6 15.0 5.0 11.5 MAX. UNITS % J/cm2 % % % % %pp % V/eNOTES 1 2 2 2 4 3, 6
Table 6 Electro-Optical Image Specifications KAI-1011CM
Notes: 1. 2. 3. 4. 5. For = 530nm wavelength, and Vsat = 350mV. Refer to typical values from Figure 19 Nominal KAI 1011CM Spectral Response. Under uniform illumination with output signal equal to 280 mV. This is the global variation in chip output for green pixels across the entire chip. It is recommended to use low pass filter with cut-off at ~ 680nm for high performance. Per color. Units: % Peak to Peak. A 200 by 200 sub ROI is used.
6.
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40%
35%
30%
Quantum Efficiency (%)
25%
20%
Red Green Blue
15%
10%
5%
0% 400
450
500
550
600
650
700
750
800
850
900
950
1000
Wavelength (nm )
Figure 19 Nominal KAI 1011CM Spectral Response
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IMAGE SENSOR SOLUTIONS
Electro-Optical for KAI-1010M
SYMBOL FF Esat QE PRNU PRNL PARAMETER Optical Fill Factor Saturation Exposure Peak Quantum Efficiency Photoresponse Non-uniformity Photoresponse Non-linearity MIN. NOM. 55.0 0.037 37 10.0 5.0 MAX. UNITS % J/cm2 % %pp % NOTES 1 2 3, 4
Table 7 Electro-Optical Image Specifications KAI-1010M
Notes: 1. 2. 3. 4. For = 550nm wavelength, and Vsat = 350mV. Refer to typical values from Figure 20 Nominal KAI-1010M Spectral Response Under uniform illumination with output signal equal to 280 mV. Units: % Peak to Peak. A 200 by 200 sub ROI is used.
0.4
0.35
0.3
Absolute Quantum Efficiency
0.25
0.2
0.15
0.1
0.05
0 400
450
500
550
600
650
700
750
800
850
900
950
1000
Wavelength (nm)
Figure 20 Nominal KAI-1010M Spectral Response
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110
100
Vertical
Quantum Efficiency (percent relative to normal incidence) 90
80
70
60
50
40
30
Horizontal
20
10
0 0 5 10 15 20 25 30 Angle from Norm al Incidence (degrees)
Figure 21 Angular Dependence of Quantum Efficiency For the curve marked "Horizontal", the incident light angle is varied in a plane parallel to the HCCD. For the curve marked "Vertical", the incident light angle is varied in a plane parallel to the VCCD.
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60
KAI-1010 Frame Rate versus Horizontal Clock Frequency
50 Dual Channel Estimated Frame Rate (Frames per Second) 40
30 Dual Channel
20 Single Channel Estimated 10 Single Channel
0 0 5 10 15 20 25 30 35 40 Horizontal Clock Frequency - (MHz)
Figure 22 Frame Rate versus Horizontal Clock Frequency
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CCD
SYMBOL Vsat Id DCDT CTE fH IL Xab Smr PARAMETER Output Saturation Voltage Dark Current Dark Current Doubling Temp Charge Transfer Efficiency Horizontal CCD Frequency Image Lag Blooming Margin Vertical Smear MIN. NOM. 350 8 0.99999 MAX. 0.5 10 40 100 100 0.01 UNITS mV nA C MHz e% NOTES 1,2,8
7
2,3 4 5 6,8 7
Table 8 CCD Image Specifications
Notes: 1. 2. 3. 4. 5. 6. Vsat is the green pixel mean value at saturation as measured at the output of the device with Xab=1. Vsat can be varied by adjusting Vsub. Measured at sensor output. With stray output load capacitance of CL = 10 pF between the output and AC ground. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance. This is the first field decay lag measured by strobe illuminating the device at (Hsat,Vsat), and by then measuring the subsequent frame's average pixel output in the dark. Xab represents the increase above the saturation-irradiance level (Hsat) that the device can be exposed to before blooming of the vertical shift register will occur. It should also be noted that Vout rises above Vsat for irradiance levels above Hsat, as shown in Figure 23. Measured under 10% (~ 100 lines) image height illumination with white light source and without electronic shutter operation and below Vsat. It should be noted that there is trade off between Xab and Vsat.
7. 8.
Output Amplifier @ VDD = 15V, VSS = 0.0V
SYMBOL Vodc Pd f-3db CL PARAMETER Output DC Offset Power Dissipation Output Amplifier Bandwidth Off-Chip Load MIN. ---NOM. 7 225 140 MAX. ---10 UNITS V mW MHz pF NOTES 1,2 3 1,4
Table 9 Output Amplifier Image Specifications
Notes: 1. 2. 3. 4. Measured at sensor output with constant current load of Iout = 5mA per output. Measured with VRD = 9v during the floating-diffusion reset interval, (R high), at the sensor output terminals. Both channels. With stray output load capacitance of CL = 10 pF between the output and AC ground.
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General
SYMBOL Vn - total DR PARAMETER Total Sensor Noise Dynamic Range MIN. NOM. 0.5 MAX. 60 UNITS mV, rms dB NOTES 1 2
Table 10 General Image Specifications
Notes: 1. 2. Includes amplifier noise and dark current shot noise at data rates of 10MHz. The number is based on the full bandwidth of the amplifier. It can be reduced when a low pass filter is used. Uses 20LOG(Vsat/Vn - total) where Vsat refers to the output saturation signal.
350
300
(Hsat, Vsat)
250 Output Signal - Vout - (mV)
200
150
100
50
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Sensor Plane Irradiance - H - (arb)
Figure 23 Typical KAI-1010M Photoresponse
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600
Vsub=8V
500
Vsub=9V
400 Output Signal - Vout - (mV)
Vsub=10V
Vsub=11V
300
Vsub=12 V Vsub=13V
200
Vsub=14V Vsub=15V
100
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Sensor Plane Irradiance - H - (arb)
Figure 24 Example of Vsat versus Vsub As Vsub is decreased, Vsat increases and anti-blooming protection decreases. As Vsub is increased, Vsat decreases and anti-blooming protection increases.
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Defect Classification
All values derived under nominal operating conditions at 40oC operating temperature. Defect Type Defective Pixel Bright Defect Cluster Defect Defect Definition Under uniform illumination with mean pixel output at 80% of Vsat, a defective pixel deviates by more than 15% from the mean value of all pixels in its section. Under dark field conditions, a bright defect deviates more than 15mV from the mean value of all pixels in its section. Two or more vertically or horizontally adjacent defective pixels. Number Allowed 12 5 0 Notes 1,2 1,2 2
Notes: 1. Sections are 252 (H) x 255 (V) pixel groups, which divide the imager into sixteen equal areas as shown below. 2. For the color device, KAI-1010CM, a defective pixel deviates by more than 15% from the mean value of all active pixels in its section with the same color.
1008,1 1008,1 1008,255 1008,510 1008,765 1008,1018 252,1018 504,1018 756,1018 1008,1018 1,1018 252,1 504,1 756,1
1,1
1,255
1,510
1,765
1,1018
1,1
Test Conditions Junction Temperature Integration Time Readout Rate (Tj) = 40oC (tint) = 70msec (treadout) = 70msec
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Climatic Requirements
ITEM Operation to Specification DESCRIPTION Temperature Humidity Operation Without Damage Storage Temperature Temperature Humidity MIN. -25 105 -50 -55 ----MAX. +40 865 +70 +70 955 UNITS
oC
CONDITIONS @ 10% 5% RH @ 36 2oC Temp. @ 10% 5% RH @ 10% 5%RH @ 49 2oC Temp.
NOTES 1, 2 1, 2 2, 3 2, 4 2, 4
%RH
oC oC
%RH
Table 11 Climatic Requirements
Notes: 1. 2. 3. 4. The image sensor shall meet the specifications of this document while operating at these conditions. The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy. The image sensor shall continue to function but not necessarily meet the specifications of this document while operating at the specified conditions. The image sensor shall meet the specifications of this document after storage for 15 days at the specified conditions.
Quality Assurance and Reliability
4.2.1 Quality Strategy: All devices will conform to the specifications stated in this document. This is accomplished through a combination of statistical process control and inspection at key points of the production process. Typical specification limits are not guaranteed but provided as a design target. For further information refer to ISS application Note MTD/PS-0292, Quality and Reliability. Replacement: All devices are warranted against failures in accordance with the Terms of Sale. This does not include failure due to mechanical and electrical causes defined as the liability of the customer below. Liability of the Supplier: A reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. Liability of the Customer: Damage from mechanical (scratches or breakage), electrostatic discharge (ESD) damage, or other electrical misuse of the device beyond the stated absolute maximum ratings, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. Cleanliness: Devices are shipped free of mobile contamination inside the package cavity. Immovable particles and scratches that are within the imager pixel area and the corresponding cover glass region directly above the pixel sites are also not allowed. The cover glass is highly susceptible to particles and other contamination. Touching the cover glass must be avoided. See ISS Application Note MTD/PS-0237, Cover Glass Cleaning for Image Sensors, for further information. ESD Precautions: Devices are shipped in static-safe containers and should only be handled at static-safe workstations. See ISS Application Note MTD/PS-0224, Electrostatic Discharge Control, for handling recommendations. Reliability: Information concerning the quality assurance and reliability testing procedures and results are available from the Image Sensor Solutions and can be supplied upon request. For further information refer to ISS Application Note MTD/PS-0292 Quality and Reliability. Test Data Retention: Image sensors shall have an identifying number traceable to a test file. Test data shall be kept for a period of 2 years after date of delivery. Mechanical: The device assembly drawing is provided as a reference. The device will conform to the published package tolerances.
4.2.2 4.2.3 4.2.4 4.2.5
4.2.6 4.2.7 4.2.8 4.2.9
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Ordering Information
Available Part Configurations Type Description KAI-1010 KAI-1010M KAI-1011CM Monochrome Monochrome with Lenslets Color with Lenslets Glass Configuration Taped On Glass or Sealed Quartz Glass Taped On Glass or Sealed AR Coated Both Sides Sealed AR Coated Both Sides
Address all inquiries and purchase orders to: Image Sensor Solutions Eastman Kodak Company Rochester, New York 14650-2010 Phone: (585) 722-4385 Fax: (585) 477-4947 www.kodak.com/go/imagers Web: E-mail: imagers@kodak.com Kodak reserves the right to change any information contained herein without notice. All information furnished by Kodak is believed to be accurate. WARNING: LIFE SUPPORT APPLICATIONS POLICY Kodak image sensors are not authorized for and should not be used within Life Support Systems without the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
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Revision Changes
No. 0 1 2 3 4 5 6 Date 02/05/1993 04/26/1993 12/20/1995 04/27/1998 09/16/1998 4/23/1999 6/18/1999 Description of Revision * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Revision 0 is the original version of the document Revision 1 changes name from KAI-1001C to KAI-1001 series and includes data on all series imagers Entire spec revised Entire spec revised Changed from KAI-1001 series to KAI-1010. Added cluster closeness specification, 4 good pixels between cluster defects. Changed defect and grades. Added frame rate table and angle QE. Added Web and e-mail references to footers. Added pixel 1,1 locator to figure 7, Pinout diagram. Corrected missing reference to figure 16 in Electro-Optical for KAI-1010CM note 2. Removed reference to KAI-1001 from both color and mono QE curves. Removed boxes around vertical and horizontal labels on angle QE figure. Removed boxes around labels on frame rate figure, added arrows from labels to curves. Corrected figure 21 Vsat versus Vsub plot to properly position labels. Added Web and e-mail references in section 4.3 ordering information. Corrected repeat table 4 entry. Corrected frame rate versus horizontal clock frequency figure. Data for dual mode was incorrect. Changed figure 6 label from Device Drawing #6 Die Placement to Device Drawing - Die Placement. Added figure 16, Fast Dump Timing. Added figure 17, Binning - 2 to 1 line binning. Added figure 18, Sample Video Waveform at 5MHz. In Appendix 1, Part Numbers, changed references from taped on glass to snap-on lid. Updated page layout. Color version of part updated to use improved material. Naming of color part changed from KAI-1010CM to KAI-1011CM. Page 13 - Added cautions pertaining to ESD and glass cleaning. Page 26 - Color PRNU value changed from 5 to 15. Units clarified to % Peak to Peak. Page 28 - Monochrome PRNU value changed from 5 to 10. Units clarified to % Peak to Peak. Page 27 - Updated color quantum efficiency graph to new KAI-1011CM. Page 35 - Updated quality Assurance and Reliability section. Page 36 - Appendix 1 replaced with Available Part Configurations.
7
10/13/1999
8
10/28/2002
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